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18-mbit (512k x 36/1m x 18) flow-through sram with nobl? architecture cy7c1371d cy7c1373d cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-05556 rev. *f revised july 09, 2007 features ? no bus latency ? (nobl ? ) architecture eliminates dead cycles between write and read cycles ? supports up to 133-mhz bus operations with zero wait states ? data is transferred on every clock ? pin-compatible and functionally equivalent to zbt? devices ? internally self-timed output buffer control to eliminate the need to use oe ? registered inputs for flow through operation ? byte write capability ? 3.3v/2.5v io power supply (v ddq ) ? fast clock-to-output times ? 6.5 ns (for 133-mhz device) ? clock enable (cen ) pin to enable clock and suspend operation ? synchronous se lf-timed writes ? asynchronous output enable ? available in jedec-standard pb-free 100-pin tqfp, pb-free and non-pb-free 119-ball bga and 165-ball fbga package. ? three chip enables for simple depth expansion ? automatic power down featur e available using zz mode or ce deselect ? ieee 1149.1 jtag-compatible boundary scan ? burst capability ? linear or interleaved burst order ? low standby power functional description [1] the cy7c1371d/cy7c1373d is a 3.3v, 512k x 36/1m x 18 synchronous flow through burst sram designed specifically to support unlimited true back-to-back read/write operations with no wait state insertion. the cy7c1371d/cy7c1373d is equipped with the advanced no bus latency (nobl) logic required to enable consecutive read/write operations with data being transferred on ev ery clock cycle. this feature dramatically improves the th roughput of data through the sram, especially in systems that require frequent write-read transitions. all synchronous inputs pass through input registers controlled by the rising edge of the clock. the clock input is qualified by the clock enable (cen ) signal, which when deasserted suspends operation and extends the previous clock cycle. maximum access delay from the cl ock rise is 6.5 ns (133-mhz device). write operations are controlled by the two or four byte write select (bw x ) and a write enable (we ) input. all writes are conducted with on-chip synchronous self-timed write circuitry. three synchronous chip enables (ce 1 , ce 2 , ce 3 ) and an asynchronous output enable (oe ) provide for easy bank selection and output tri-state co ntrol. to avoid bus contention, the output drivers are synchronousl y tri-stated during the data portion of a write sequence. selection guide 133 mhz 100 mhz unit maximum access time 6.5 8.5 ns maximum operating current 210 175 ma maximum cmos standby current 70 70 ma note: 1. for best-practices recommendations, please refer to the cypress application note system design guidelines on www.cypress.com. [+] feedback
cy7c1371d cy7c1373d document #: 38-05556 rev. *f page 2 of 29 logic block diagram ? cy7c1371d (512k x 36) logic block diagram ? cy7c1373d (1m x 18) c mode bw a bw b we ce1 ce2 ce3 oe read logic dqs dqp a dqp b dqp c dqp d memory array e input register bw c bw d address register write registry and data coherency control logic burst logic a0' a1' d1 d0 q1 q0 a0 a1 adv/ld ce adv/ld c clk cen write drivers d a t a s t e e r i n g s e n s e a m p s write address register a0, a1, a o u t p u t b u f f e r s e zz sleep control c mode bw a bw b we ce1 ce2 ce3 oe read logic dqs dqp a dqp b memory array e input register address register write registry and data coherency control logic burst logic a0' a1' d1 d0 q1 q0 a0 a1 adv/ld ce adv/ld c clk cen write drivers d a t a s t e e r i n g s e n s e a m p s write address register a0, a1, a o u t p u t b u f f e r s e zz sleep control [+] feedback
cy7c1371d cy7c1373d document #: 38-05556 rev. *f page 3 of 29 pin configurations 100-pin tqfp pinout a a a a a1 a0 nc/288m nc/144m v ss v dd nc/36m a a a a a a dqp b dq b dq b v ddq v ss dq b dq b dq b dq b v ss v ddq dq b dq b v ss nc v dd dq a dq a v ddq v ss dq a dq a dq a dq a v ss v ddq dq a dq a dqp a dqp c dq c dq c v ddq v ss dq c dq c dq c dq c v ss v ddq dq c dq c nc v dd nc v ss dq d dq d v ddq v ss dq d dq d dq d dq d v ss v ddq dq d dq d dqp d a a ce 1 ce 2 bw d bw c bw b bw a ce 3 v dd v ss clk we cen oe a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 a a adv/ld zz mode nc/72m cy7c1371d byte a byte b byte d byte c a [+] feedback
cy7c1371d cy7c1373d document #: 38-05556 rev. *f page 4 of 29 100-pin tqfp pinout pin configurations (continued) a a a a a1 a0 nc/288m nc/144m v ss v dd nc/36m a a a a a a a nc nc v ddq v ss nc dqp a dq a dq a v ss v ddq dq a dq a v ss nc v dd dq a dq a v ddq v ss dq a dq a nc nc v ss v ddq nc nc nc nc nc nc v ddq v ss nc nc dq b dq b v ss v ddq dq b dq b nc v dd nc v ss dq b dq b v ddq v ss dq b dq b dqp b nc v ss v ddq nc nc nc a a ce 1 ce 2 nc nc bw b bw a ce 3 v dd v ss clk we cen oe a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 a a adv/ld zz mode nc/72m cy7c1373d byte a byte b a [+] feedback
cy7c1371d cy7c1373d document #: 38-05556 rev. *f page 5 of 29 pin configurations (continued) 234567 1 a b c d e f g h j k l m n p r t u v ddq nc/576m nc/1g dqp c dq c dq d dq c dq d aa aav ddq ce 2 a dq c v ddq dq c v ddq v ddq v ddq dq d dq d nc/144m nc v ddq v dd clk v dd v ss v ss v ss v ss v ss v ss v ss v ss nc nc nc nc tdo tck tdi tms nc/36m nc/72m nc/288m v ddq v ddq v ddq aaa a ce 3 a a a a a a a0 a1 dq a dq c dq a dq a dq a dq b dq b dq b dq b dq b dq b dq b dq a dq a dq a dq a dq b v dd dq c dq c dq c v dd dq d dq d dq d dq d adv/ld nc ce 1 oe a we v ss v ss v ss v ss v ss v ss v ss v ss dqp a mode dqp d dqp b bw b bw c nc v dd nc bw a nc cen bw d zz 2 34567 1 a b c d e f g h j k l m n p r t u v ddq nc/576m nc/1g nc dq b dq b dq b dq b aa aav ddq ce 2 a nc v ddq nc v ddq v ddq v ddq nc nc nc/144m nc/72m v ddq v dd clk v dd v ss v ss v ss v ss v ss v ss v ss v ss nc nc nc nc tdo tck tdi tms a a nc/288m v ddq v ddq v ddq anc/36ma a ce 3 a a a a a a a0 a1 dq a dq b nc nc dq a nc dq a dq a nc nc dq a nc dq a nc dq a nc dq a v dd nc dq b nc v dd dq b nc dq b nc adv/ld nc ce 1 oe a we v ss v ss v ss v ss v ss v ss v ss v ss nc mode dqp b dqp a nc bw b nc v dd nc bw a nc cen nc zz cy7c1373d (1mx 18) a a 119-ball bga pinout cy7c1371d (512k x 36) [+] feedback
cy7c1371d cy7c1373d document #: 38-05556 rev. *f page 6 of 29 pin configurations (continued) 165-ball fbga pinout cy7c1371d (512k x 36) 234 567 1 a b c d e f g h j k l m n p r tdo nc/576m nc/1g dqp c dq c dqp d nc dq d ce 1 bw b ce 3 bw c cen a ce2 dq c dq d dq d mode nc dq c dq c dq d dq d dq d nc/36m nc/72m v ddq bw d bw a clk we v ss v ss v ss v ss v ddq v ss v dd v ss v ss v ss v ss v ss v ss v ddq v ddq nc v ddq v ddq v ddq v ddq a a v dd v ss v dd v ss v ss v ddq v dd v ss v dd v ss v dd v ss v ss v ss v dd v dd v ss v dd v ss v ss nc tck v ss tdi a a dq c v ss dq c v ss dq c dq c nc v ss v ss v ss v ss nc v ss a1 dq d dq d nc/144m nc v ddq v ss tms 891011 nc/288m a a adv/ld nc oe a nc v ss v ddq nc dqp b v ddq v dd dq b dq b dq b nc dq b nc dq a dq a v dd v ddq v dd v ddq dq b v dd nc v dd dq a v dd v ddq dq a v ddq v dd v dd v ddq v dd v ddq dq a v ddq a a v ss a a a dq b dq b dq b zz dq a dq a dqp a dq a a v ddq a a0 a v ss nc cy7c1373d (1m x 18) 234 567 1 a b c d e f g h j k l m n p r tdo nc/576m nc/1g nc nc dqp b nc dq b ce 1 nc ce 3 bw b cen a ce2 nc dq b dq b mode nc dq b dq b nc nc nc nc/36m nc/72m v ddq nc bw a clk we v ss v ss v ss v ss v ddq v ss v dd v ss v ss v ss v ss v ss v ss v ddq v ddq nc v ddq v ddq v ddq v ddq a a v dd v ss v dd v ss v ss v ddq v dd v ss v dd v ss v dd v ss v ss v ss v dd v dd v ss v dd v ss v ss nc tck v ss tdi a a dq b v ss nc v ss dq b nc nc v ss v ss v ss v ss nc v ss a1 dq b nc nc/144m nc v ddq v ss tms 891011 nc/288m a a adv/ld a oe a nc v ss v ddq nc dqp a v ddq v dd nc dq a dq a nc nc nc dq a nc v dd v ddq v dd v ddq dq a v dd nc v dd nc v dd v ddq dq a v ddq v dd v dd v ddq v dd v ddq nc v ddq a a v ss a a a dq a nc nc zz dq a nc nc dq a a v ddq a a0 a v ss nc a a [+] feedback
cy7c1371d cy7c1373d document #: 38-05556 rev. *f page 7 of 29 pin definitions name io description a 0 , a 1 , a input- synchronous address inputs used to select one of the address locations . sampled at the rising edge of the clk. a [1:0] are fed to the two-bit burst counter. bw a , bw b bw c , bw d input- synchronous byte write inputs, active low . qualified with we to conduct writes to the sram. sampled on the rising edge of clk. we input- synchronous write enable input, active low . sampled on the rising edge of clk if cen is active low. this signal must be asserted low to initiate a write sequence. adv/ld input- synchronous advance/load input . used to advance the on-chip address counter or load a new address. when high (and cen is asserted low) the internal burst counter is advanced. when low, a new address can be loaded into the device for an access. after being deselected, adv/ld must be driven low to load a new address. clk input- clock clock input . used to capture all synchronous inputs to the device. clk is qualified with cen . clk is only recognized if cen is active low. ce 1 input- synchronous chip enable 1 input, active low . sampled on the rising edge of clk. used in conjunction with ce 2 and ce 3 to select/deselect the device. ce 2 input- synchronous chip enable 2 input, active high . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 3 to select/desel ect the device. ce 3 input- synchronous chip enable 3 input, active low . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 2 to select/deselect the device. oe input- asynchronous output enable, asynchronous input, active low . combined with the synchronous logic block inside the device to control the direction of the io pins. when low, the io pins are allowed to behave as outputs. when deasserted high, io pins are tri-stated, and act as input data pins. oe is masked during the data portion of a write sequence, during th e first clock when emerging from a deselected state, when the device has been deselected. cen input- synchronous clock enable input, active low . when asserted low the clock signal is recognized by the sram. when deasserted high the clock signal is masked. while deasserting cen does not deselect the device, use cen to extend the previous cycle when required. zz input- asynchronous zz ?sleep? input . this active high input places the device in a non-time critic al ?sleep? condition with data integrity preserved. for normal operation, this pin has to be low or left floating. zz pin has an internal pull down. dq s io- synchronous bidirectional data io lines . as inputs, they feed into an on-chip data register that is triggered by the rising edge of clk. as outputs, they deliver t he data contained in the memory location specified by the addresses presented during the previous cl ock rise of the read cycle. the direction of the pins is controlled by oe . when oe is asserted low, the pins behave as outputs. when high, dq s and dqp [a:d] are placed in a tri-state condition.the out puts are automatically tri-stated during the data portion of a write sequence, during the fi rst clock when emerging from a deselected state, and when the device is deselected, regardless of the state of oe . dqp x io- synchronous bidirectional data parity io lines. functionally, these signals are identical to dq s . mode input strap pin mode input. selects the burst order of the device. when tied to gnd selects linear burst sequence. when tied to v dd or left floating selects interleaved burst sequence. v dd power supply power supply inputs to the core of the device . v ddq io power supply power supply for the io circuitry . v ss ground ground for the device . [+] feedback
cy7c1371d cy7c1373d document #: 38-05556 rev. *f page 8 of 29 functional overview the cy7c1371d/cy7c1373d is a synchronous flow through burst sram designed specifically to eliminate wait states during write-read transitions. all synchronous inputs pass through input registers controlled by the rising edge of the clock. the clock signal is qualified with the clock enable input signal (cen ). if cen is high, the clock signal is not recog- nized and all internal states are maintained. all synchronous operations are qualified with cen . maximum access delay from the clock rise (t cdv ) is 6.5 ns (133-mhz device). accesses can be initiated by asserting all three chip enables (ce 1 , ce 2 , ce 3 ) active at the rising edge of the clock. if clock enable (cen ) is active low and adv/ld is asserted low, the address presented to the device is latched. the access can either be a read or write operation, depending on the status of the write enable (we ). bw x can be used to conduct byte write operations. write operations are qualified by the write enable (we ). all writes are simplified with on-chip synchronous self-timed write circuitry. three synchronous chip enables (ce 1 , ce 2 , ce 3 ) and an asynchronous output enable (oe ) simplify depth expansion. all operations (reads, writes, and deselects) are pipelined. adv/ld must be driven low after the device has been deselected to load a new address for the next operation. single read accesses a read access is initiated when these conditions are satisfied at clock rise: ?cen is asserted low ?ce 1 , ce 2 , and ce 3 are all asserted active ? the write enable input signal we is deasserted high ?adv/ld is asserted low. the address presented to the address inputs is latched into the address register and presented to the memory array and control logic. the control logic determines that a read access is in progress and allows the requested data to propagate to the output buffers. the data is available within 6.5 ns (133-mhz device) provided oe is active low. after the first clock of the read access, the output buffers are controlled by oe and the internal control logic. oe must be driven low in order for the device to drive out the requested data. on the subsequent clock, another oper ation (read/write/deselect) can be initiated. when the sram is deselected at clock rise by one of the chip enable signals, its output is tri-stated immediately. burst read accesses the cy7c1371d/cy7c1373d has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four reads without reasserting the address inputs. adv/ld must be driven low to load a new address into the sram, as described in the single read access section above. the sequence of the burst counter is deter- mined by the mode input signal. a low input on mode selects a linear burst mode, a high selects an interleaved burst sequence. both burst counters use a 0 and a 1 in the burst sequence, and wraps around when incremented sufficiently. a high input on adv/ld increments the internal burst counter regardless of the state of chip enable inputs or we . we is latched at the beginning of a bu rst cycle. therefore, the type of access (read or write) is maintained throughout the burst sequence. single write accesses write access are initiated w hen the following conditions are satisfied at clock rise: (1) cen is asserted low, (2) ce 1 , ce 2 , and ce 3 are all asserted active, and (3) the write signal we is asserted low. the address presented to the address bus is loaded into the address register. the write signals are latched into the control logic block. the data lines are automatically tri-stated regar dless of the state of the oe input signal. this allows the external logic to present the data on dqs and dqp x . on the next clock rise the data presented to dqs and dqp x (or a subset for byte write o perations, see truth table for tdo jtag serial output synchronous serial data-out to the jtag circuit . delivers data on the negative edge of tck. if the jtag feature is not being used, this pin must be left unconnected. this pin is not available on tqfp packages. tdi jtag serial input synchronous serial data-in to the jtag circuit . sampled on the rising edge of tc k. if the jtag feature is not being used, this pin can be left floating or connected to v dd through a pull up resistor. this pin is not available on tqfp packages. tms jtag serial input synchronous serial data-in to the jtag circuit . sampled on the rising edge of tc k. if the jtag feature is not being used, this pin can be disconnected or connected to v dd . this pin is not available on tqfp packages. tck jtag- clock clock input to the jtag circuitry . if the jtag feature is not being used, this pin must be connected to v ss . this pin is not available on tqfp packages. nc ? no connects . not internally connected to the die. nc/ (36 m, 72 m, 144 m, 288m, 576m, 1g)are address expansion pins and are not internally connected to the die. pin definitions (continued) name io description [+] feedback
cy7c1371d cy7c1373d document #: 38-05556 rev. *f page 9 of 29 details) inputs is latched into the device and the write is complete. additional accesses (read/write/deselect) can be initiated on this cycle. the data written during the write operation is controlled by bw x signals. the cy7c1371d/cy7c1373d provides byte write capability that is descri bed in the truth table. asserting the write enable input (we ) with the selected byte write select input selectively writes to only the desired bytes. bytes not selected during a byte write operation remains unaltered. a synchronous self-timed write mechanism has been provided to simplify the write operations . byte write capability has been included to greatly simplify read/modify/write sequences, which can be reduced to simple byte write operations. because the cy7c1371d/cy7c1373d is a common io device, data must not be driven into the device while the outputs are active. the output enable (oe ) can be deasserted high before presenting data to the dqs and dqp x inputs. doing so tri-states the output drivers. as a safety precaution, dqs and dqp x are automatically tri-stated during the data portion of a write cycle, regardless of the state of oe . burst write accesses the cy7c1371d/cy7c1373d has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four write operat ions without reasserting the address inputs. adv/ld must be driven low to load the initial address, as described in th e single write access section above. when adv/ld is driven high on the subsequent clock rise, the chip enables (ce 1 , ce 2 , and ce 3 ) and we inputs are ignored and the burst counte r is incremented. the correct bw x inputs must be driven in each cycle of the burst write, to write the correct bytes of data. sleep mode the zz input pin is an asynchronous input. asserting zz places the sram in a power conservation ?sleep? mode. two clock cycles are required to enter into or exit from this ?sleep? mode. while in this mode, data integrity is guaranteed. accesses pending when entering the ?sleep? mode are not considered valid nor is the completion of the operation guaranteed. the device must be deselected prior to entering the ?sleep? mode. ce 1 , ce 2 , and ce 3 , must remain inactive for the duration of t zzrec after the zz input returns low. interleaved burst address table (mode = floating or v dd ) first address a1: a0 second address a1: a0 third address a1: a0 fourth address a1: a0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 linear burst address table (mode = gnd) first address a1: a0 second address a1: a0 third address a1: a0 fourth address a1: a0 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 zz mode electrical characteristics parameter description test conditions min max unit i ddzz sleep mode standby current zz > v dd ? 0.2v 80 ma t zzs device operation to zz zz > v dd ? 0.2v 2t cyc ns t zzrec zz recovery time zz < 0.2v 2t cyc ns t zzi zz active to sleep current t his parameter is sampled 2t cyc ns t rzzi zz inactive to exit sleep curre nt this parameter is sampled 0 ns [+] feedback
cy7c1371d cy7c1373d document #: 38-05556 rev. *f page 10 of 29 truth table [2, 3, 4, 5, 6, 7, 8] operation address used ce 1 ce 2 ce 3 zz adv/ld we bw x oe cen clk dq deselect cycle none h x x l l x x x l l->h tri-state deselect cycle none x x h l l x x x l l->h tri-state deselect cycle none x l x l l x x x l l->h tri-state continue deselect cycle none x x x l h x x x l l->h tri-state read cycle (begin burst) external l h l l l h x l l l->h data out (q) read cycle (continue burst) next x x x l h x x l l l->h data out (q) nop/dummy read (begin burst) external l h l l l h x h l l->h tri-state dummy read (continue burst) next x x x l h x x h l l->h tri-state write cycle (begin burst) external l h l l l l l x l l->h data in (d) write cycle (continue burst) next x x x l h x l x l l->h data in (d) nop/write abort (begin burst) none l h l l l l h x l l->h tri-state write abort (continue burst) next x x x l h x h x l l->h tri-state ignore clock edge (stall) current x x x l x x x x h l->h ? sleep mode none x x x h x x x x x x tri-state partial truth table for read/write [2, 3, 9] function (cy7c1371d) we bw a bw b bw c bw d read hxxxx write no bytes written l h h h h write byte a ? (dq a and dqp a )llhhh write byte b ? (dq b and dqp b )lhlhh write byte c ? (dq c and dqp c )lhhlh write byte d ? (dq d and dqp d )lhhhl write all bytes lllll partial truth table for read/write [2, 3, 9] function (cy7c1373d) we bw a bw b read hxx write - no bytes written l h h write byte a ? (dq a and dqp a )llh write byte b ? (dq b and dqp b )lhl write all bytes l l l notes: 2. x = ?don't care.? h = logic high, l = logic low. bw x = 0 signifies at least one byte write select is active, bw x = valid signifies that the desired byte write selects are asserted, see truth table for details. 3. write is defined by bw x , and we . see truth table for read/write. 4. when a write cycle is detected, all ios are tri-stated, even during byte writes. 5. the dqs and dqp x pins are controlled by the current cycle and the oe signal. oe is asynchronous and is not sampled with the clock. 6. cen = h, inserts wait states. 7. device powers up deselected and the ios in a tri-state condition, regardless of oe . 8. oe is asynchronous and is not sampled with the clock rise. it is masked internally during write cyc les. during a read cycle dqs a nd dqp x = tri-state when oe is inactive or when the device is deselected, and dqs and dqp x = data when oe is active. 9. table only lists a partial listing of the byte write combinations. any combination of bw x is valid appropriate write is based on which byte write is active. [+] feedback
cy7c1371d cy7c1373d document #: 38-05556 rev. *f page 11 of 29 ieee 1149.1 serial boundary scan (jtag) the cy7c1371d/cy7c1373d incorporates a serial boundary scan test access port (tap).this part is fully compliant with 1149.1. the tap operates using jedec-standard 3.3v or 2.5v io logic levels. the cy7c1371d/cy7c1373d contains a tap controller, instruction register, boundary sc an register, bypass register, and id register. disabling the jtag feature it is possible to operate the sram without using the jtag feature. to disable the tap controller, tck must be tied low (v ss ) to prevent clocking of the device. tdi and tms are inter- nally pulled up and may be unconnected. they may alternately be connected to v dd through a pull up resistor. tdo must be left unconnected. upon power up, the device is up in a reset state which does not interfere with the operation of the device. the 0/1 next to each state repr esents the value of tms at the rising edge of tck. test access port (tap) test clock (tck) the test clock is used only with the tap controller. all inputs are captured on the rising edge of tck. all outputs are driven from the falling edge of tck. test mode select (tms) the tms input is used to give commands to the tap controller and is sampled on the rising edge of tck. it is allowable to leave this ball unconnected if the tap is not used. the ball is pulled up internally, resulting in a logic high level. test data-in (tdi) the tdi ball is used to serially input information into the registers and can be connected to the input of any of the registers. the register between tdi and tdo is chosen by the instruction that is loaded into the tap instruction register. for information on loading the instruction register, see tap controller state diagram. tdi is internally pulled up and can be unconnected if the tap is unused in an application. tdi is connected to the most significant bit (msb) of any register. (see tap controller block diagram.) test data-out (tdo) the tdo output ball is used to serially clock data-out from the registers. the output is active depending upon the current state of the tap state machine. the output changes on the falling edge of tck. tdo is connected to the least significant bit (lsb) of any register. (see tap controller state diagram.) performing a tap reset a reset is performed by forcing tms high (v dd ) for five rising edges of tck. this reset does not affect the operation of the sram and may be performed while the sram is operating. at power up, the tap is reset internally to ensure that tdo comes up in a high-z state. tap registers registers are connected between the tdi and tdo balls and allow data to be scanned into and out of the sram test circuitry. only one register can be selected at a time through the instruction register. data is serially loaded into the tdi ball on the rising edge of tck. data is output on the tdo ball on the falling edge of tck. instruction register three-bit instructions can be seri ally loaded into the instruction register. this register is loaded when it is placed between the tdi and tdo balls as shown in the tap controller block diagram. upon power up, the instruction register is loaded with the idcode instruction. it is also loaded with the idcode tap controller state diagram test-logic reset run-test/ idle select dr-scan select ir-scan capture-dr shift-dr capture-ir shift-ir exit1-dr pause-dr exit1-ir pause-ir exit2-dr update-dr exit2-ir update-ir 1 1 1 0 1 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 tap controller block diagram bypass register 0 instruction register 0 1 2 identification register 0 1 2 29 30 31 . . . boundary scan register 0 1 2 . . x . . . selection circuitry tck tms tap controller tdi td o selection circuitry [+] feedback
cy7c1371d cy7c1373d document #: 38-05556 rev. *f page 12 of 29 instruction if the controller is placed in a reset state as described in the previous section. when the tap controller is in the capture-ir state, the two least significant bits are loaded with a binary ?01? pattern to allow for fault isolation of the board level serial test data path. bypass register to save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. the bypass register is a single-bit register that can be placed between the tdi and tdo balls. this allows data to be shifted through the sram with minimal delay. the bypass register is set low (v ss ) when the bypass instruction is executed. boundary scan register the boundary scan register is connected to all the input and bidirectional balls on the sram. the boundary scan register is lo aded with the contents of the ram io ring when the tap co ntroller is in the capture-dr state and is then placed between the tdi and tdo balls when the controller is moved to the shift-dr state. the extest, sample/preload and sample z instructions can be used to capture the contents of the io ring. the boundary scan order tables show the order in which the bits are connected. each bit corresponds to one of the bumps on the sram package. the msb of the register is connected to tdi and the lsb is connected to tdo. identification (id) register the id register is loaded with a vendor-specific, 32-bit code during the capture-dr state when the idcode command is loaded in the instruction regi ster. the idcode is hardwired into the sram and can be shifted out when the tap controller is in the shift-dr state. the id register has a vendor code and other information described in the identification register definitions table. tap instruction set overview eight different instructions are possible with the three bit instruction register. all combinations are listed in the instruction codes table. three of these instructions are listed as reserved and must not be used. the other five instruc- tions are described in detail below. instructions are loaded into the tap controller during the shift-ir state when the instruction register is placed between tdi and tdo. during this state, instructions are shifted through the instruction register through the tdi and tdo balls. to execute the instruction after it is shifted in, the tap controller needs to be moved into the update-ir state. extest the extest instruction enables the preloaded data to be driven out through the system output pins. this instruction also selects the boundary scan register to be connected for serial access between the tdi and tdo in the shift-dr controller state. idcode the idcode instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. it also places the instruction register between the tdi and tdo balls and allows the idcode to be shifted out of the device when the tap controller enters the shift-dr state. the idcode instruction is loaded into the instruction register upon power up or whenever the tap controller is supplied a test logic reset state. sample z the sample z instruction causes the boundary scan register to be connected between the tdi and tdo balls when the tap controller is in a shift-dr state. it also places all sram outputs into a high-z state. sample/preload sample/preload is a 1149.1 mandatory instruction. when the sample/preload instruct ions are loaded into the instruction register and the tap controller is in the capture-dr state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. the user must be aware that th e tap controller clock can only operate at a frequency up to 20 mhz, while the sram clock operates more than an order of magnitude faster. because there is a large difference in the clock frequencies, it is possible that during the capture-dr state, an input or output undergoes a transition. the ta p may then try to capture a signal while in transition (metastable state). this does not harm the device, but there is no guarantee as to the value that is captured. repeatable results may not be possible. to guarantee that the boundary scan register captures the correct value of a signal, the sram signal must be stabilized long enough to meet the tap c ontroller's capture setup plus hold times (t cs and t ch ). the sram clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a sample/p reload instruction. if this is an issue, it is still possible to capture all other signals and simply ignore the value of the ck and ck captured in the boundary scan register. after the data is captured, it is possible to shift out the data by putting the tap into the shift-dr state. this places the bound- ary scan register between the tdi and tdo pins. preload allows an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells pri- or to the selection of another boundary scan test operation. the shifting of data for the sample and preload phases can occur concurrently when required?that is, while data captured is shifted out, the pr eloaded data can be shifted in. bypass when the bypass instruction is loaded in t he instruction register and the tap is placed in a shift-dr state, the bypass register is placed between the tdi and tdo balls. the advantage of the bypass instructio n is that it shortens the [+] feedback
cy7c1371d cy7c1373d document #: 38-05556 rev. *f page 13 of 29 boundary scan path when multiple devices are connected together on a board. extest output bus tri-state ieee standard 1149.1 mandates that the tap controller be able to put the output bu s into a tri-state mode. the boundary scan register has a special bit located at bit #85 (for 119-bga package) or bit #89 (for 165-fbga package). when this scan cell, called the ?extest output bus tri-state,? is latched into the preload register during the ?update-dr? state in the tap controller, it directly controls the state of the output (q-bus) pins, when the extest is entered as the current instruction. when high, it enables the output buffers to drive the output bus. when low, this bit places the output bus into a high-z condition. this bit can be set by entering the sample/preload or extest command, and then shifting the desired bit into that cell, during the ?shift-dr? stat e. during ?update-dr,? the value loaded into that shift-register cell latches into the preload register. when the extest instruction is entered, this bit directly controls th e output q-bus pins. note that this bit is preset high to enable the output when the device is powered-up, and also when the tap controller is in the ?test-logic-reset? state. reserved these instructions are not im plemented but are reserved for future use. do not use these instructions. tap timing t tl test clock (tck) 123456 t est mode select (tms) t th test data-out (tdo) t cyc test data-in (tdi) t tmsh t tmss t tdih t tdis t tdox t tdov dont care undefined [+] feedback
cy7c1371d cy7c1373d document #: 38-05556 rev. *f page 14 of 29 tap ac switching characteristics over the operating range [10, 11] parameter description min max unit clock t tcyc tck clock cycle time 50 ns t tf tck clock frequency 20 mhz t th tck clock high time 20 ns t tl tck clock low time 20 ns output times t tdov tck clock low to tdo valid 10 ns t tdox tck clock low to tdo invalid 0 ns setup times t tmss tms setup to tck clock rise 5 ns t tdis tdi setup to tck clock rise 5 ns t cs capture setup to tck rise 5 ns hold times t tmsh tms hold after tck clock rise 5 ns t tdih tdi hold after clock rise 5 ns t ch capture hold after clock rise 5 ns notes: 10. t cs and t ch refer to the setup and hold time requirements of latching data from the boundary scan register. 11. test conditions are spec ified using the load in tap ac test conditions. t r /t f = 1 ns. [+] feedback
cy7c1371d cy7c1373d document #: 38-05556 rev. *f page 15 of 29 3.3v tap ac test conditions input pulse levels ............................................... .v ss to 3.3v input rise and fall times ......... .......................................... 1 ns input timing referenc e levels ...........................................1.5v output reference levels...................................................1.5v test load termination supply vo ltage...............................1.5v 2.5v tap ac test conditions input pulse level................................................... v ss to 2.5v input rise and fall time .....................................................1 ns input timing reference levels... ..................................... .1.25v output reference levels .......... ...................................... 1.25v test load termination supply voltage ............................ 1.25v 3.3v tap ac output load equivalent tdo 1.5v 20pf z = 50 ? o 50 ? 2.5v tap ac output load equivalent tdo 1.25v 20pf z = 50 ? o 50 ? (0c < ta < +70c; vdd = 3.3v 0.165v unless otherwise noted) [12] parameter description description conditions min max unit v oh1 output high voltage i oh = ?4.0 ma v ddq = 3.3v 2.4 v i oh = ?1.0 ma v ddq = 2.5v 2.0 v v oh2 output high voltage i oh = ?100 a v ddq = 3.3v 2.9 v v ddq = 2.5v 2.1 v v ol1 output low voltage i ol = 8.0 ma v ddq = 3.3v 0.4 v i ol = 1.0 ma v ddq = 2.5v 0.4 v v ol2 output low voltage i ol = 100 a v ddq = 3.3v 0.2 v v ddq = 2.5v 0.2 v v ih input high voltage v ddq = 3.3v 2.0 v dd + 0.3 v v ddq = 2.5v 1.7 v dd + 0.3 v v il input low voltage v ddq = 3.3v ?0.5 0.7 v v ddq = 2.5v ?0.3 0.7 v i x input load current gnd < v in < v ddq ?5 5 a note: 12. all voltages referenced to v ss (gnd). [+] feedback
cy7c1371d cy7c1373d document #: 38-05556 rev. *f page 16 of 29 identification register definitions instruction field cy7c1371d (512k x 36) cy7c1373d (1m x 18) description revision number (31:29) 000 000 describes the version number device depth (28:24) 01011 01011 reserved for internal use device width (23:18) 001001 001001 defines memory type and architecture cypress device id (17:12) 100101 010101 defines width and density cypress jedec id code (11:1) 00000110100 00000110100 allows unique identification of sram vendor id register presence indicator (0) 1 1 ind icates the presence of an id register scan register sizes register name bit size (x36) bit size (x18) instruction 3 3 bypass 1 1 id 32 32 boundary scan order (119-ball bga package) 85 85 boundary scan order (165-ball fbga package) 89 89 identification codes instruction code description extest 000 captures io ring contents. places the boundary scan register between tdi and tdo. forces all sram outputs to high-z state. idcode 001 loads the id register with the vendor id code and places the register between tdi and tdo. this operation does not affect sram operations. sample z 010 captures io ring contents. places the boundary scan register between tdi and tdo. forces all sram output drivers to a high-z state. reserved 011 do not use: this instruct ion is reserved for future use. sample/preload 100 captures io ring contents. plac es the boundary scan register between tdi and tdo. does not affect sram operation. reserved 101 do not use: this instruct ion is reserved for future use. reserved 110 do not use: this instruct ion is reserved for future use. bypass 111 places the bypass register between tdi and tdo. this operation does not affect sram operations. [+] feedback
cy7c1371d cy7c1373d document #: 38-05556 rev. *f page 17 of 29 119-ball bga boundary scan order [13, 14] bit # ball id bit # ball id bit # ball id bit # ball id 1 h4 23 f6 45 g4 67 l1 2 t4 24e7 46a4 68m2 3t5 25d7 47g3 69n1 4 t6 26h7 48c3 70p1 5r5 27g6 49b2 71k1 6 l5 28e6 50b3 72l2 7r629d651a373 n2 8u630c752c274p2 9 r7 31b7 53a2 75r3 10 t7 32 c6 54 b1 76 t1 11 p6 33 a6 55 c1 77 r1 12 n7 34 c5 56 d2 78 t2 13 m6 35 b5 57 e1 79 l3 14 l7 36 g5 58 f2 80 r2 15 k6 37 b6 59 g1 81 t3 16 p7 38 d4 60 h2 82 l4 17 n6 39 b4 61 d1 83 n4 18 l6 40 f4 62 e2 84 p4 19 k7 41 m4 63 g2 85 internal 20 j5 42 a5 64 h1 21 h6 43 k4 65 j3 22 g7 44 e4 66 2k notes: 13. balls which are nc (no connect) are pre-set low. 14. bit# 85 is pre-set high. [+] feedback
cy7c1371d cy7c1373d document #: 38-05556 rev. *f page 18 of 29 165-ball bga boundary scan order [13, 15] bit # ball id bit # ball id bit # ball id 1 n6 31 d10 61 g1 2n7 32c11 62d2 3 n10 33 a11 63 e2 4p11 34b11 64f2 5p8 35a10 65g2 6r8 36b10 66h1 7r9 37a9 67h3 8p938b968j1 9 p10 39 c10 69 k1 10 r10 40 a8 70 l1 11 r11 41 b8 71 m1 12 h11 42 a7 72 j2 13 n11 43 b7 73 k2 14 m11 44 b6 74 l2 15 l11 45 a6 75 m2 16 k11 46 b5 76 n1 17 j11 47 a5 77 n2 18 m10 48 a4 78 p1 19 l10 49 b4 79 r1 20 k10 50 b3 80 r2 21 j10 51 a3 81 p3 22 h9 52 a2 82 r3 23 h10 53 b2 83 p2 24 g11 54 c2 84 r4 25 f11 55 b1 85 p4 26 e11 56 a1 86 n5 27 d11 57 c1 87 p6 28 g10 58 d1 88 r6 29 f10 59 e1 89 internal 30 e10 60 f1 note: 15. bit# 89 is pre-set high. [+] feedback
cy7c1371d cy7c1373d document #: 38-05556 rev. *f page 19 of 29 maximum ratings exceeding maximum ratings may impair the useful life of the device. these user guidelines are not tested. storage temperature ............. .............. ...... ?65c to +150c ambient temperature with power applied........... .............. .............. ...... ?55c to +125c supply voltage on v dd relative to gnd........ ?0.5v to +4.6v supply voltage on v ddq relative to gnd ...... ?0.5v to +v dd dc voltage applied to outputs in tri-state........................................... ?0.5v to v ddq + 0.5v dc input voltage ................................... ?0.5v to v dd + 0.5v current into outputs (low).... ..................................... 20 ma static discharge voltage......... ........... ............ .......... > 2001v (mil-std-883, method 3015) latch up current.................................................... > 200 ma operating range range ambient temperature v dd v ddq commercial 0c to +70c 3.3v ? 5%/+10% 2.5v ? 5% to v dd industrial ?40c to +85c electrical characteristics over the operating range [16, 17] parameter description test conditions min max unit v dd power supply voltage 3.135 3.6 v v ddq io supply voltage for 3.3v io 3.135 v dd v for 2.5v io 2.375 2.625 v v oh output high voltage for 3.3v io, i oh = ?4.0 ma 2.4 v for 2.5v io, i oh = ?1.0 ma 2.0 v v ol output low voltage for 3.3v io, i ol = 8.0 ma 0.4 v for 2.5v io, i ol = 1.0 ma 0.4 v v ih input high voltage [16] for 3.3v io 2.0 v dd + 0.3v v for 2.5v io 1.7 v dd + 0.3v v v il input low voltage [16] for 3.3v io ?0.3 0.8 v for 2.5v io ?0.3 0.7 v i x input leakage current except zz and mode gnd v i v ddq ?5 5 a input current of mode input = v ss ?30 a input = v dd 5 a input current of zz input = v ss ?5 a input = v dd 30 a i dd v dd operating supply current v dd = max., i out = 0 ma, f = f max = 1/t cyc 7.5 ns cycle, 133 mhz 210 ma 10 ns cycle, 100 mhz 175 ma i sb1 automatic ce power down current?ttl inputs v dd = max, device deselected, v in v ih or v in v il f = f max , inputs switching 7.5 ns cycle, 133 mhz 140 ma 10 ns cycle, 100 mhz 120 ma i sb2 automatic ce power down current?cmos inputs v dd = max, device deselected, v in 0.3v or v in > v dd ? 0.3v, f = 0, inputs static all speeds 70 ma i sb3 automatic ce power down current?cmos inputs v dd = max, device deselected, or v in 0.3v or v in > v ddq ? 0.3v f = f max , inputs switching 7.5 ns cycle, 133 mhz 130 ma 10 ns cycle, 100 mhz 110 ma i sb4 automatic ce power down current?ttl inputs v dd = max, device deselected, v in v dd ? 0.3v or v in 0.3v , f = 0, inputs static all speeds 80 ma notes: 16. overshoot: v ih (ac) < v dd +1.5v (pulse width less than t cyc /2), undershoot: v il (ac) > ?2v (pulse width less than t cyc /2). 17. t power-up : assumes a linear ramp from 0v to v dd (min.) within 200 ms. during this time v ih < v dd and v ddq < v dd . [+] feedback
cy7c1371d cy7c1373d document #: 38-05556 rev. *f page 20 of 29 capacitance [18] parameter description test conditions 100 tqfp package 119 bga package 165 fbga package unit c in input capacitance t a = 25 c, f = 1 mhz, v dd = 3.3v v ddq = 2.5v 589pf c clk clock input capacitance 5 8 9 pf c io input/output capacitance 5 8 9 pf thermal resistance [18] parameter description test conditions 100 tqfp package 119 bga package 165 fbga package unit ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, according to eia/jesd51. 28.66 23.8 20.7 c/w jc thermal resistance (junction to case) 4.08 6.2 4.0 c/w ac test loads and waveforms output r = 317 ? r = 351 ? 5pf including jig and scope (a) (b) output r l = 50 ? z 0 = 50 ? v t = 1.5v 3.3v all input pulses v ddq gnd 90% 10% 90% 10% 1ns 1ns (c) output r = 1667 ? r = 1538 ? 5pf including jig and scope (a) (b) output r l = 50 ? z 0 = 50 ? v t = 1.25v 2.5v all input pulses v ddq gnd 90% 10% 90% 10% 1ns 1ns (c) 3.3v io test load 2.5v io test load note: 18. tested initially and after any design or process change that may affect these parameters. [+] feedback
cy7c1371d cy7c1373d document #: 38-05556 rev. *f page 21 of 29 switching characteristics over the operating range [23, 24] parameter description 133 mhz 100 mhz unit min max min max t power [19] 11ms clock t cyc clock cycle time 7.5 10 ns t ch clock high 2.1 2.5 ns t cl clock low 2.1 2.5 ns output times t cdv data output valid after clk rise 6.5 8.5 ns t doh data output hold af ter clk rise 2.0 2.0 ns t clz clock to low-z [20, 21, 22] 2.0 2.0 ns t chz clock to high-z [20, 21, 22] 4.0 5.0 ns t oev oe low to output valid 3.2 3.8 ns t oelz oe low to output low-z [20, 21, 22] 00ns t oehz oe high to output high-z [20, 21, 22] 4.0 5.0 ns setup times t as address setup before clk rise 1.5 1.5 ns t als adv/ld setup before clk rise 1.5 1.5 ns t wes we , bw x setup before clk rise 1.5 1.5 ns t cens cen setup before clk rise 1.5 1.5 ns t ds data input setup before clk rise 1.5 1.5 ns t ces chip enable setup before clk rise 1.5 1.5 ns hold times t ah address hold after clk rise 0.5 0.5 ns t alh adv/ld hold after clk rise 0.5 0.5 ns t weh we , bw x hold after clk rise 0.5 0.5 ns t cenh cen hold after clk rise 0.5 0.5 ns t dh data input hold after clk rise 0.5 0.5 ns t ceh chip enable hold after clk rise 0.5 0.5 ns notes: 19. this part has a voltage regulator internally; t power is the time that the power needs to be supplied above v dd (minimum) initially, before a read or write operation can be initiated. 20. t chz , t clz , t oelz , and t oehz are specified with ac test conditions shown in part (b) of ac test loads. transition is measured 200 mv from steady-state vo ltage. 21. at any voltage and temperature, t oehz is less than t oelz and t chz is less than t clz to eliminate bus contention between srams when sharing the same data bus. these specifications do not imply a bus cont ention condition, but reflect parameters gu aranteed over worst case user conditions . device is designed to achieve high-z prior to low-z under the same system conditions. 22. this parameter is sampled and not 100% tested. 23. timing reference level is 1.5v when v ddq = 3.3v and is 1.25v when v ddq = 2.5v. 24. test conditions shown in (a) of ac test loads unless otherwise noted. [+] feedback
cy7c1371d cy7c1373d document #: 38-05556 rev. *f page 22 of 29 switching waveforms read/write waveforms [25, 26, 27] write d(a1) 123 456789 clk t cyc t cl t ch 10 ce t ceh t ces we cen t cenh t cens bw x adv/ld t ah t as address a1 a2 a3 a4 a5 a6 a7 t dh t ds dq command t clz d(a1) d(a2) q(a4) q(a3) d(a2+1) t doh t chz t cdv write d(a2) burst write d(a2+1) read q(a3) read q(a4) burst read q(a4+1) write d(a5) read q(a6) write d(a7) deselect oe t oev t oelz t oehz dont care undefined d(a5) t doh q(a4+1) d(a7) q(a6) notes: 25. for this waveform zz is tied low. 26. when ce is low, ce 1 is low, ce 2 is high and ce 3 is low. when ce is high, ce 1 is high or ce 2 is low or ce 3 is high. 27. order of the burst sequence is determined by the status of the mode (0 = linear, 1 = interleaved). burst operations are opti onal. [+] feedback
cy7c1371d cy7c1373d document #: 38-05556 rev. *f page 23 of 29 nop, stall and deselect cycles [25, 26, 28] switching waveforms (continued) read q(a3) 456 78910 a3 a4 a5 d(a4) 123 clk ce we cen bw [a:d] adv/ld address dq command write d(a4) stall write d(a1) read q(a2) stall nop read q(a5) deselect continue deselect dont care undefined t chz a1 a2 q(a2) d(a1) q(a3) t doh q(a5) note: 28. the ignore clock edge or stall cycle (clock 3) illustrates cen being used to create a pause. a wr ite is not performed during this cycle. [+] feedback
cy7c1371d cy7c1373d document #: 38-05556 rev. *f page 24 of 29 zz mode timing [29, 30] switching waveforms (continued) t zz i supply clk zz t zzrec all inputs (except zz) dont care i ddzz t zzi t rzzi outputs (q) high-z deselect or read only notes: 29. device must be deselected when entering zz mode. see truth t able for all possible signal c onditions to deselect the device. 30. dqs are in high-z when exiting zz sleep mode. [+] feedback
cy7c1371d cy7c1373d document #: 38-05556 rev. *f page 25 of 29 ordering information not all of the speed, package and temper ature ranges are available. please c ontact your local sales representative or visit www.cypress.com for actual products offered. speed (mhz) ordering code package diagram part and package type operating range 133 cy7c1371d-133axc 51-85050 100-pin thin quad flat pack (14 x 20 x 1.4 mm) pb-free commercial cy7c1373d-133axc cy7c1371d-133bgc 51-8511 5 119-ball grid array (14 x 22 x 2.4 mm) cy7c1373d-133bgc cy7c1371d-133bgxc 51-85115 1 19-ball grid array (14 x 22 x 2.4 mm) pb-free cy7c1373d-133bgxc cy7c1371d-133bzc 51-85180 165 -ball fine-pitch ball grid array (13 x 15 x 1.4 mm) cy7c1373d-133bzc cy7c1371d-133bzxc 51-85180 165-ball fine-pitch ball grid array (13 x 15 x 1.4 mm) pb-free cy7c1373d-133bzxc cy7c1371d-133axi 51-85050 100-pin thin quad flat pack (14 x 20 x 1.4 mm) pb-free lndustrial cy7c1373d-133axi cy7c1371d-133bgi 51-8511 5 119-ball grid array (14 x 22 x 2.4 mm) cy7c1373d-133bgi cy7c1371d-133bgxi 51-85115 1 19-ball grid array (14 x 22 x 2.4 mm) pb-free cy7c1373d-133bgxi cy7c1371d-133bzi 51-85180 165 -ball fine-pitch ball grid array (13 x 15 x 1.4 mm) cy7c1373d-133bzi cy7c1371d-133bzxi 51-85180 165-ball fine-pitch ball grid array (13 x 15 x 1.4 mm) pb-free cy7c1373d-133bzxi 100 cy7c1371d-100axc 51-85050 100-pin thin quad flat pack (14 x 20 x 1.4 mm) pb-free commercial cy7c1373d-100axc cy7c1371d-100bgc 51-8511 5 119-ball grid array (14 x 22 x 2.4 mm) cy7c1373d-100bgc cy7c1371d-100bgxc 51-85115 1 19-ball grid array (14 x 22 x 2.4 mm) pb-free cy7c1373d-100bgxc cy7c1371d-100bzc 51-85180 165 -ball fine-pitch ball grid array (13 x 15 x 1.4 mm) cy7c1373d-100bzc cy7c1371d-100bzxc 51-85180 165-ball fine-pitch ball grid array (13 x 15 x 1.4 mm) pb-free cy7c1373d-100bzxc cy7c1371d-100axi 51-85050 100-pin thin quad flat pack (14 x 20 x 1.4 mm) pb-free lndustrial cy7c1373d-100axi cy7c1371d-100bgi 51-8511 5 119-ball grid array (14 x 22 x 2.4 mm) cy7c1373d-100bgi cy7c1371d-100bgxi 51-85115 1 19-ball grid array (14 x 22 x 2.4 mm) pb-free cy7c1373d-100bgxi cy7c1371d-100bzi 51-85180 165 -ball fine-pitch ball grid array (13 x 15 x 1.4 mm) cy7c1373d-100bzi cy7c1371d-100bzxi 51-85180 165-ball fine-pitch ball grid array (13 x 15 x 1.4 mm) pb-free cy7c1373d-100bzxi [+] feedback
cy7c1371d cy7c1373d document #: 38-05556 rev. *f page 26 of 29 package diagrams figure 1. 100-pin thin plastic quad flatpack (14 x 20 x 1.4 mm), 51-85050 note: 1. jedec std ref ms-026 2. body length dimension does not include mold protrusion/end flash mold protrusion/end flash shall not exceed 0.0098 in (0.25 mm) per side 3. dimensions in millimeters body length dimensions are max plastic body size including mold mismatch 0.300.08 0.65 20.000.10 22.000.20 1.400.05 121 1.60 max. 0.05 min. 0.600.15 0 min. 0.25 0-7 (8x) stand-off r 0.08 min. typ. 0.20 max. 0.15 max. 0.20 max. r 0.08 min. 0.20 max. 14.000.10 16.000.20 0.10 see detail a detail a 1 100 30 0 5 1 3 51 80 81 gauge plane 1.00 ref. 0.20 min. seating plane 51-85050-*b [+] feedback
cy7c1371d cy7c1373d document #: 38-05556 rev. *f page 27 of 29 figure 2. 119-ball bga (14 x 22 x 2.4 mm) (51-85115) package diagrams (continued) 1.27 20.32 2 16 5 4 37 l e a b d c h g f k j u p n m t r 12.00 19.50 30 typ. 2.40 max. a1 corner 0.70 ref. u t r p n m l k j h g f e d c a b 21 43 65 7 ?1.00(3x) ref. 7.62 22.000.20 14.000.20 1.27 0.600.10 c 0.15 c b a 0.15(4x) ?0.05 m c ?0.750.15(119x) ?0.25mcab seating plane 0.900.05 3.81 10.16 0.25 c 0.56 51-85115-*b [+] feedback
cy7c1371d cy7c1373d document #: 38-05556 rev. *f page 28 of 29 ? cypress semiconductor corporation, 2004-2007. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent o r other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. nobl and no bus latency are trademarks of cypress semiconduc tor corporation. zbt is a trademark of integrated device technology, inc. all product and company names mentioned in this document are the trademarks of their respective holders. figure 3. 165-ball fbga (13 x 15 x 1.4 mm) (51-85180) package diagrams (continued) a 1 pin 1 corner 15.000.10 13.000.10 7.00 1.00 ?0.50 (165x) ?0.25mcab ?0.05 m c b a 0.15(4x) 0.350.06 seating plane 0.530.05 0.25 c 0.15 c pin 1 corner top view bottom view 2 3 4 5 6 7 8 9 10 10.00 14.00 b c d e f g h j k l m n 11 11 10 9 8 67 5 4 3 2 1 p r p r k m n l j h g f e d c b a a 15.000.10 13.000.10 b c 1.00 5.00 0.36 -0.06 +0.14 1.40 max. solder pad type : non-solder mask defined (nsmd) notes : package weight : 0.475g jedec reference : mo-216 / design 4.6c package code : bb0ac 51-85180-*a [+] feedback
cy7c1371d cy7c1373d document #: 38-05556 rev. *f page 29 of 29 document history page document title: cy7c1371d/cy7c1373d 18-mbit (512k x 36/1 mbit x 18) flow through sram with nobl? architecture document number: 38-05556 rev. ecn no. issue date orig. of change description of change ** 254513 see ecn rkf new data sheet *a 288531 see ecn syt edited description under ?ieee 1149.1 serial boundary scan (jtag)? for non-compliance with 1149.1 removed 117 mhz speed bin added pb-free information for 100-pin tqfp, 119 bga and 165 fbga packages added comment of ?pb-free bg packages availability? below the ordering infor- mation *b 326078 see ecn pci address expansion pins/balls in the pinouts for all packages are modified according to jedec standard added description on extest output bus tri-state changed description on the tap instruction set overview and extest changed ja and jc for tqfp package from 31 and 6 c/w to 28.66 and 4.08 c/w respectively changed ja and jc for bga package from 45 and 7 c/w to 23.8 and 6.2 c/w respectively changed ja and jc for fbga package from 46 and 3 c/w to 20.7 and 4.0 c/w respectively modified v ol, v oh test conditions removed comment of ?pb-free bg package s availability? below the ordering infor- mation updated ordering information table *c 345117 see ecn pci updated ordering information table changed from preliminary to final *d 416321 see ecn nxr changed address of cypress semiconductor corporation on page# 1 from ?3901 north first street? to ?198 champion court? in the partial truth table for read/write on page # 10, the bw a of write byte a ? (dq a and dqp a ) and bw b of write byte b ? (dq b and dqp b ) has been changed from h to l changed the description of i x from input load current to input leakage current on page# 20 changed the ix current values of mode on page # 20 from -5 a and 30 a to -30 a and 5 a changed the ix current values of zz on page # 20 from -30 a and 5 a to -5 a and 30 a changed v ih < v dd to v ih < v dd on page # 20 replaced package name column with package diagram in the ordering information table updated ordering information table *e 475677 see ecn vkn added the maximum rating for supply voltage on v ddq relative to gnd changed t th , t tl from 25 ns to 20 ns and t tdov from 5 ns to 10 ns in tap ac switching characteristics table. updated the ordering information table. *f 1274734 see ecn vkn/aesa correct ed typo in the ?nop, stall and deselect cycles? waveform [+] feedback

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